This invention relates generally to packet data communications and more specifically to interfaces within packet data communication networks.
Internet capacity, along with the speed of packet transmission within the Internet, is increasing at an incredibly fast pace, requiring fast packet forwarding decisions in the range of several million packets per second. This growth of the Internet is fostering the introduction of new protocols and variations on existing protocols to enable the implementation of larger and higher capacity networks. While the design of the protocols has traditionally relied upon software programs for implementation within routers, allowing for a great deal of flexibility, the speed of conventional Central Processing Unit (CPU) hardware and architectures is no longer capable of handling the rates of traffic required.
The higher speeds associated with data packet forwarding within routers can be accommodated with custom hardware with the use of Application Specific Integrated Circuits (ASICs), but the relative inflexibility of hardware solutions and their longer development cycle make them less attractive in this continuously changing environment. In fact, the increased sophistication needed to support Internet Protocol (IP) Quality of Service (QoS) handling is difficult to provide in hardware, for it requires a substantial amount of processing power. As well, the limited expected lifespan of data routing and forwarding products makes low development costs and short time-to-market more important factors than the actual product cost.
To overcome this problem of implementing purely software or purely hardware solutions, software programmable computers or micro-controllers have been used in the past to perform packet forwarding. The problem with such implementations now is that the conventional computer architectures used within these devices impose severe limits, especially in their memory subsystems, and are not directly suitable for processing data packets at the rates required.
Therefore, a flexible service-independent interface is required that can be used for packet forwarding. This interface should be completely re-configurable so as to adapt with changing protocols while supporting a variety of different protocols and services at any one time, each service possibly operating at different transmission rates. Preferably, this implementation should not lock the interface into using a particular processor or prevent the interface from being scaled to an arbitrary number of processors, but should be kept flexible while keeping the development cost low.
It is an object of the present invention to overcome the disadvantages of the prior art and, in particular, to provide an apparatus whereby data information units can be efficiently transferred.
According to a first aspect, the present invention provides an interface apparatus capable of being coupled between first and second data apparatuses, the interface apparatus comprising at least one processor and at least three memory devices; and wherein each of the memory devices is arranged to be coupled to the first data apparatus during different respective time periods to input and store data information units from the first data apparatus; each of the memory devices is arranged to be coupled to the processor during different respective time periods to process the stored data information units with use of the processor; and each of the memory devices is arranged to be coupled to the second data apparatus during different respective time periods to output the processed data information units to the second data apparatus.
According to a second aspect, the present invention provides an interface apparatus arranged to be coupled between first and second data apparatuses, the interface apparatus comprising at least one ingress processor, at least three ingress memory devices, at least one egress processor, and at least three egress memory devices; wherein each of the ingress memory devices is arranged to be coupled to the first data apparatus during different respective time periods to input and store first data information units from the first data apparatus; each of the ingress memory devices is arranged to be coupled to the ingress processor during different respective time periods to process the stored first data information units with use of the ingress processor; and each of the ingress memory devices is arranged to be coupled to the second data apparatus during different respective time periods to output the processed first data information units to the second data apparatus; and wherein each of the egress memory devices is arranged to be coupled to the second data apparatus during different respective time periods to input and store second data information units from the second data apparatus; each of the egress memory devices is arranged to be coupled to the egress processor during different respective time periods to process the stored second data information units with use of the egress processor; and each of the egress memory devices is arranged to be coupled to the first data apparatus during different respective time periods to output the processed second data information units to the first data apparatus.
According to a third aspect, the present invention provides in an interface apparatus arranged to be coupled between first and second data apparatuses, a method of transferring data information units between the first and second apparatuses comprising the steps of: coupling each of at least three memory devices to the first data apparatus at different respective first times; inputting data information units from the first data apparatus to each of the memory devices during different respective first time periods starting at the different respective first times; uncoupling each of the memory devices from the first data apparatus and coupling each of the memory devices to a processor at different respective second times; processing the stored data information units within each of the memory devices with use of the processor during different respective second time periods starting at the different respective second times; uncoupling each of the memory devices from the processor and coupling each of the memory devices to the second data apparatus at different respective third times; and outputting the processed data information units within each of the memory devices to the second data apparatus during different respective third time periods starting at the different respective third times.